Continued efforts are directed toward the miniaturization of circuits so that more and more devices can be fabricated on a single chip or wafer. This applies both to MOS-type circuits, such as CMOS circuits, as well as to bipolar circuits. Indeed, there exists many applications in which both CMOS and bipolar circuits are utilized on the same chip. However, the integration of the bipolar and CMOS (BiCMOS) family of circuits is not easily accomplished, because of the diverse fabrication steps generally required by each such type of circuit. Heretofore, the integration of CMOS and bipolar circuits has been generally implemented by first fabricating one circuit type, and then the other. As can be appreciated, the processing of such type of wafer becomes extremely complicated due to the number and the complexity of steps.
Not only are the circuit fabricating steps of a BiCMOS circuit made complex due to the integration of each family of circuit, but the circuit isolation techniques have also become more complex. For example, the PMOS and NMOS devices of a CMOS circuit are typically isolated by thick field oxide structures. These surface planar transistor devices are readily adapted for isolation by the field oxide. A popular type of isolation for vertical bipolar transistors comprises deep trench isolation structures. When combining the CMOS and bipolar circuit families, it has been advantageous and an expedient technique to first fabricate the thick field oxide insulation for the CMOS circuits, and thereafter fabricate the trench isolation structures for the bipolar section of the chip, or vice versa. Aside from requiring a large number of processing steps for fabricating the field oxide and trench isolation structures, the field oxide structures which isolate CMOS devices yet require a substantial amount of lateral wafer area, due to "bird's beak" and "bird's head" extensions. These noted lateral extensions tend to encroach upon adjacent circuits, and thus the designer must take special precautions in spacing the active or passive circuits a prescribed distance away from the field oxide isolation pattern.
From the foregoing, it can be seen that a need exists for an improved technique for simultaneously fabricating bipolar and CMOS isolation structures. A further need exists for a CMOS isolation structure which alleviates encroachment problems, thereby allowing circuits to be more densely packed together. Yet another need exists for a circuit isolation technique which minimizes the fabrication steps and reduces the complexity of the overall process, but which yet utilizes conventional silicon fabrication steps.